Optimization of Power in Flip-Flop Group using Clock Gating and Power Gating with Variable Body-Bias Technique

Optimization of Power in Flip-Flop Group using Clock Gating and Power Gating with Variable Body-Bias Technique
Authors:TASKEEN KAUR DHANJAL, APARNA KARWAL

Abstract: Energy dissipation is a very critical parameter that has to be taken into account during the design of Very Large Scale Integration (VLSI) circuits. With the rapid progress in semiconductor technology, chip density and operation frequency have increased, making the power consumption in battery-operated portable devices a major concern. Integrated Circuit (IC) power dissipation consists of different components depending on the circuit operating mode. First, the switching or dynamic power component dominates during the active mode of operation. Second, there are two primary leakage sources, the active component and the standby leakage component. Clock gating and power gating proves to be very effective solutions for reducing dynamic and active leakage power respectively. The two techniques are coupled in such a way that the clock gating information is used to drive the control signal of power-gating circuitry. First, a technique named Optimized Bus-Specific-Clock-Gating (OBSC) is introduced which reduces the problem of gated flip-flop selection by appropriate selection of subset of flip-flops. Then another technique named Run Time Power Gating (RTPG) is proposed for power gating the combinational logics performing redundant operations. The proposed shift registers are designed up to the layout level with 1V Power supply in 0.18um technology and simulated using Tanner Tools.

Keywords: Clock Gating, Power Dissipation, Power Gating, OBSC, RTPG.

I. INTRODUCTION

Today's consumer demands more functionality, energy efficient device and optimized power devices as time goes, so in order to optimize power of a device the simplest control technique is to shut off the clock of the sequential block of the device when there is no function required from that section for some duration With the smaller geometries in Deep Sub-Micron (DSM) technology, the number of gates that need to be integrated on a single chip, power density, and total power are increasing rapidly. The scaling of process technologies to nanometer regime has resulted in a rapid increase in leakage power dissipation [1]. Integrated Circuit (IC) power dissipation consists of different components depending on the circuit operating mode. First, the switching or dynamic power component dominates during the active

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Recursive Approach to the Design of CSLA D-Latch Based Parallel Self Timed Adder

Recursive Approach to the Design of CSLA D-Latch Based Parallel Self Timed Adder

Authors:K.SRI HARI, GOPI ALOKAM, L.CHANDRA SEKHAR

Abstract: This paper presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multi bit binary addition. The Carry Select Adder is used in many systems to relieve the problem of carry propagation delay which is happen by independently generating multiple carries and to generate the sum then select a carry. Due to uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input However, the CSLA is not time efficient, then by the multiplexers the final sum and carry are selected. The basic idea of this work is to achieve high speed and low power consumption by use Binary to Excess-1 Converter (BEC) instead of RCA in the regular CSLA. At the same time to further reduce the power consumption, a new approach of CSLA with D LATCH is proposed in this project. In the proposed scheme, before the calculation of-final-sum the carry select that is specified as CS operation is scheduled. For logic optimization of Carry selection bit patterns of two anticipating carry words that is corresponding to cin = 0 and 1 and fixed cin bits are used. Using optimized logic units an efficient CSLA design is obtained. The proposed Carry Select Adder design involves significantly less area and power than the recently proposed BEC-based CSLA.

Keywords: CSLA, RCA, BEC, D-LATCH, Self-Timed Adder.

I. INTRODUCTION

Now days the portability of the electronic component have rapid growth, the low power arithmetic circuit has become very important in VLSI industry. In The digital signal processor (DSP) main building block is the Multiplier-Accumulator (MAC) unit. Full Adder used as a part of the MAC unit uses full-adder as part which can significantly influences the efficiency of total system. Full Adder circuit is necessary for low power application due to the reduction in power consumption. The basic operation Carry Select Adder (CSLA) is parallel computation. CSLA generates many carriers and partial sum. Multiplexers select the final sum and carry. In the CSLA architecture, Addition operation usually trembles widely the overall performance of digital systems and a crucial arithmetic function. The adders are most widely used in the electronic applications.

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Implementation of Error Correcting Codes for Low Area and Power Optimized Applications

Implementation of Error Correcting Codes for Low Area and Power Optimized Applications
Authors:SUNKARA KISHORE, G.SIVARAMAKRISHNA, K. CHINNAMALLA REDDY

Abstract: AS CMOS technology scales down to nano scale and memories are combined with an increasing number of electronic systems, the soft error rate in memory cells is rapidly increasing. Although single bit upset is a major concern about memory reliability, multiple cell upsets (MCUs) have become a serious reliability concern in some memory applications which requires error correction. In order to make memory cells as fault-tolerant as possible, some error correction codes (ECCs) have been widely used to protect memories. For example, the Bose Chaudhuri Hocquenghem codes, Reed–Solomon codes, and punctured difference set (PDS) codes have been used to deal with MCUs in memories. But these codes require more area, power overheads since the encoding and decoding circuits are more complex in these complicated codes. In this project due to introduction of butterfly-formed weight accumulator (BWA) block to enhance the performance with less power consumption is proposed for efficient error correction.

Keywords: Butterfly-Formed Weight Accumulator, Error-Correcting Codes, VERILOG, XILINX ISE.

                                                             INTRODUCTION


     Error detection and correction (EDAC) techniques are used to ensure that data is correct and has not been corrupted, either by hardware failures or by noise occurring during transmission or a data read operation from Memory. There are many different error correction codes in existence. The reason for the different codes being used in different applications has to do with the historical development of the data storage, the types of data errors occurring, and the overhead associated with each of the error detection techniques. The basic concept of error detection and correction method is as follow 1.Networks must be able to transfer data from one system to another without data can be corrupted during transmission. For reliable communication, errors must be detected and corrected. Any error-correcting code can be used for error detection and correction. Error-correcting code (ECC) or forward error correction (FEC) code is a system of adding redundant data, or parity data,


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