Logical Effort Based Dual Mode Logic Gates
Keywords: Dual Mode Logic, Static Mode, Dynamic Mode, Logical Effort Methodology, Digital Schematic Tool (DSCH).
Abstract: Logic optimization and timing estimations are basic tasks for digital circuit designers. Dual Mode Logic (DML)
allows operation in two modes such as static and dynamic modes. DML gates can be switched between these two modes on
feature very low power dissipation in the static mode and high speed of operation in dynamic mode which is achieved at the
expense of increased power dissipation. We introduce the logical effort (LE) methodology for the CMOS-based family. The
proposed methodology allows path length, delay and power optimization for number of stages with load. Logical effort is the
transistor sizing optimization methodology reduces the delay and power with number of stages with any static logic gate. The
proposed optimization is shown for dual mode logic gates with logical effort using Digital Schematic Tool (DSCH).
INTRODUCTION
Logic Optimization And Timing Estimations Are Basic
Tasks For Digital Circuit Designers. The Logical Effort (LE)
Method Was First Presented By Sutherland [1],[10] For Easy
And Fast Evaluation And Optimization Of Delay In CMOS
Logic Paths. Because Of Its Elegance, The LE Method Has
Become A Very Popular Tool For Designing And Education
Purposes And Is Adopted To Be The Basis For Several
Computer-Aided-Design Tools. Although LE Is Mainly Used
For Standard CMOS Logic, It Is Also Shown to Be Useful
for Other Logic Families, Such As The Pass Transistor Logic
[8].The Novel Dual Mode Logic (DML), Which Provides the
designer with a very high level of switching between two
modes of operation: 1) static and 2) dynamic modes.
